The present disclosure relates to semiconductor structures and methods of fabricating the same. More particularly, the present disclosure relates to multi-gated fully depleted non-planar semiconductor devices, such as, for example, finFETs, having a stressed channel caused by stress memorization. The present disclosure also provides methods of fabricating such non-planar semiconductor devices.
A multi-gated transistor is a metal oxide semiconductor field effect transistor (MOSFET) in which a gate electrode is placed on two or three sides of a channel or is wrapped around the channel, with a gate dielectric separating the gate electrode and the channel. A double gate finFET utilizes a double gate configuration in which the gate electrode is placed on two opposite sides of the channel. In a triple gate FET, the gate electrode is placed on one more side of a typically rectangular channel of the transistor. In a quadruple gate EET or a wrapped gate FET or a surround gate FET, the gate electrode is placed on four sides of the channel. The thin, undoped channel of a finFET device enhances the controllability of the finFET channel compared to a planar bulk MOSFET device or a PDSOI MOSFET device. The improved control of the channel allows smaller device dimensions with less short channel effects as well as larger electrical current that can be switched at high speeds. A finFET device has faster switching times, equivalent or higher current density, and much improved short channel control than mainstream complementary metal oxide semiconductor (CMOS) technology utilizing similar critical dimensions.
In a typical finFET structure, at least one horizontal channel on a vertical sidewall is provided within a semiconductor “fin” that is set sideways, or edgewise, upon a substrate. Typically, the fin comprises a single crystalline semiconductor material with a substantially rectangular cross-sectional area. The height of the fin, which fixes the device width, is typically greater than the width of the fin to enable higher on-current per unit area of semiconductor used for the finFET structure. In order to obtain desirable control of short channel effects (SCEs), the semiconductor fin is made thin enough in a device channel region to ensure forming fully depleted semiconductor devices. Typically, the thickness, or the horizontal width, of a fin in a finFET is less than two-thirds of its gate length in order to obtain good control of the short channel effects.
An inverted U-shaped gate electrode often straddles a central section of the semiconductor fin and covers the gate dielectric layer. In a typical double gate finFET, a gate dielectric layer and a gate conductor are located upon each of the two semiconductor fin sidewalls facing each other. A hard mask of substantial thickness is typically located between the top surface of the fin and the top portion of the inverted U-shaped gate electrode such that the top surface of the fin is not controlled directly by the portion of the gate electrode above it. In a typical triple gate finFET, a gate electrode of an inverted U shape is typically located upon the two semiconductor fin sidewalls and also upon the top surface of the fin structure. The top surface of the fin is separated from the top portion of the gate electrode only by a gate dielectric layer and is thus controlled by the gate electrode.
Doping is performed by techniques such as ion implantation or dopant diffusion on the source and drain regions, which are the end portions of the semiconductor fin, to deliver halo, extension, and source/drain doping while using the gate electrode or other masking layer as a mask on the channel region of the device.
Such three-dimensional geometry, which is provided by multi-gated fully depleted non-planar semiconductor devices, and the need for continued external resistance (Rext) scaling necessitate merging of the source/drain regions by growing an epitaxial semiconductor layer on the source/drain regions, or some other intimate electrical contact to the fin sidewalls. However, this same piece of real estate has competing claims for a stress liner in order to modulate the strain parallel and along the channel.